1. Field of the Invention
The present invention is related to circuit simulation and verification methods and software, and more particularly to array modeling methods and software that verify performance of the array.
2. Description of Related Art
Full circuit simulation is not typically performed by simultaneously modeling each cell in an array during design verification. Since the amount of computation time and memory required increases geometrically with the array dimension, timing analysis is usually performed by using lumped parameter models for inactive cells during a particular timing pass. The use of a model for the inactive cell loading effect reduces the accuracy of the simulation, and in high speed memory designs leads to less than ideal designs and over-specified margins.
The worst-case read performance of an array (or sub-array if the array is partitioned) is typically dictated by cells along the edges of the array, since the worst-case arrival time delay of the wordline from the boundary of the array and the worst-case propagation time from the output of the cell pass device(s) to the output circuit, generally a read circuit, will always have a shortest and longest value located at opposing corners of the array. Since an array is defined by the progression of wordlines along one edge and bit-lines along the other the corner cell corresponding to the shortest bitline and wordline should have the minimum delay and the opposite corner, the maximum delay.
However, since the wordline driver circuits have non-uniform delay, the worst-case read delay values (both min and max) can occur anywhere along the edges of the array. Further, if the read circuits are non-uniform or have non-uniform paths to a downstream point at which they must be timed, then the worst-case read delay values could occur at any cell within the array. Both min and max delays are critical in designs that are timed to provide the shortest consecutive read cycles, because the data cannot be timed to arrive too early or too late.
Since the write performance is dependent on the relative arrival of both a data value on a bitline and a strobe value on a wordline, the worst-case write conditions also do not always occur at the edge of the array, since the worst-case word line and data bitline delay from their respective driver circuits can occur at any combination of row and column.
Simulation of each cell in an array is a time-consuming process, as in current analysis software, each propagation of signals within a cell typically requires full execution of the simulation code for each cell unless the cell is completely removed from the model, which is why the above-mentioned lumped-parameter model technique is often used. Some attempts have been made to model arrays by removing all of the cells except for the edge cells. However, as noted above, write failures can be missed due to the dependence of a successful write on the relative arrival of the strobe and data value. Further, removal of all of the center cells alters the bitline and wordline loading, resulting in timing deviations that can miss write failures and potentially read failures.
Such reduction is extremely desirable, since full simulation of an J by K array has a computation time of the cell computation time multiplied by J*K, in essence an N-squared burden as array dimension increases. Full simulation of only the edge cells requires only 2*(J+K)−4, which is an N-order computational burden as array dimension increases.
Therefore, it would be desirable to provide a design verification method for arrays that can reduce the analysis time while accurately verifying read and write performance of an entire array.